1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a storage electrode of the capacitor structure in a semiconductor memory such as a DRAM (dynamic random access memory) and a method for forming the same.
2. Description of Related Art
With advancement of the semiconductor device manufacturing technology, the integration density of the DRAM is increasing more and more and the microfabrication of the DRAM is advancing more and more. This can be realized by reducing the area per memory cell, since an array of memory cells occupies a major portion of a chip area. However, when the area per memory cell is reduced, a storage capacitance of each memory cell for storing data is correspondingly reduced.
As a means for increasing the storage capacitance in a limited area for a unitary memory cell for the purpose of overcoming the above mentioned problem, it is a general practice to increase a surface area of a storage electrode (lower electrode) of the capacitor. For increasing the surface area, a stacked capacitor, a trench capacitor, and a stacked-and-trench combined capacitor have been proposed. Among these proposed capacitors, since the stacked capacitor can be formed by a forming method which is simpler than that for forming the trench capacitor, many researches have been conducted for the stacked capacitor.
However, in the DRAM of 64 Mbits or more, a method of increasing the height of the storage electrode of a conventional simple three-dimensional stacked capacitor for the purpose of obtaining a necessary surface area, has already become difficult to ensure a sufficient capacitance. In addition, an absolute step difference (level difference) between a memory cell zone and a peripheral circuit zone becomes large, with the result that it is difficult to pattern a wiring conductor layer formed to extend over both the memory cell zone and the peripheral circuit zone, in particular, by a photolithography. Under this circumstance, various modified three-dimensional stacked capacitors have been proposed by JP-A-05-067747 and its corresponding U.S. Pat. No. 5,164,881, JP-A-06-204428 and its corresponding U.S. Pat. No. 5,389,568 and JP-A-05-267614 and its corresponding U.S. Pat. No. 5,150,276, the contents of which are incorporated by reference in their entirety into this application.
Among these proposed stacked capacitors, a stacked capacitor of a cylindrical structure for the DRAM, proposed by JP-A-06-204428 and U.S. Pat. No. 5,389,568, utilizes not only an inner wall surface but also an outer wall surface as a surface area, and therefore, is a structure suitable to a memory cell for a higher integration density memory.
Now, this structure will be described with reference to FIGS. 1A to 1H, which are diagrammatic sectional views for illustrating a semiconductor memory having a cylindrical structure stacked capacitor and a method for manufacturing the same.
As shown in FIG. 1A, a surface of a p-type silicon substrate 1 is divided into an active region and an inactive region by forming a field oxide film 2 on the surface of a p-type silicon substrate 1 by a conventional device isolation process. In the active region, a pair of transistors are formed to have a bit line B and a drain region D formed under the bit line B, in common to the pair of transistors. Each of the transistors has a source region S formed separately form the common drain region D and a gate electrode 3 formed on a gate insulator formed on a region between the common drain D and the individual source region S. The above mentioned elements are formed in a conventional semiconductor device manufacturing process.
Furthermore, in order to isolate the transistors thus formed, from a conducting layer which will be formed at a later step, an interlayer insulator film 4 is formed to cover the whole surface, and a BPSG (borophosphosilicate glass) film 5 is grown on the interlayer insulator film 4 by a lower pressure CVD (chemical vapor deposition) or an atmospheric pressure CVD and a reflow processing is conducted.
Then, a silicon nitride film (SiN) film 6 is grown on the whole surface, and a capacitor contact hole 7 is formed at a position of a cell node of the memory cell by means of a photolithography and an anisotropic etching.
Succeedingly, as shown in FIG. 1B, a first polysilicon film 12 is deposited to cover the whole surface of the silicon nitride film 6 and the capacitor contact hole 7, and as shown in FIG. 1C, a NSG (non-doped silicate glass) film 12 is further deposited to completely fill the capacitor contact hole 7 and to cover an upper surface of the first polysilicon film 12. Then, a stacked structure composed of the NSG film 13 and the first polysilicon film 12 is patterned to the shape of a storage electrode of the stacked capacitor (cylindrical shape) as indicated by the arrow Y1.
Thereafter, as shown in FIG. 1E, a second polysilicon film 17 is deposited on the whole surface, and then, as shown in FIG. 1F, the whole surface is anisotropically etched so that a side wall 18 of the second polysilicon film 17 is formed on a side surface of the patterned stacked structure of the first polysilicon layer 12 and the NSG film 13.
Furthermore, as shown in FIG. 1G, only the NSG film 12 is removed by an ammon fluoride (ammonium fluoride) solution, so that a surface of the storage electrode composed of the patterned first polysilicon film 12 and the side wall 18 of the remaining second polysilicon 17, is exposed. Thus, the storage electrode designated by Reference Numeral 8 in FIG. 1H is formed, which is in contact with the silicon substrate 1 (specifically, the source region S) through the capacitor contact hole 7 and which extends in a horizontal direction on the upper surface of the silicon nitride film 6 (constituting the insulator film) and further extends in an upward vertical direction at an arbitrary position.
Thereafter, a dielectric material film 9 is formed on the whole surface, and then, a third polysilicon film is deposited on the whole surface as a plate electrode 10 of the stacked capacitor. Thus, the capacitor structure of the DRAM is completed.
Incidentally, JP-A-05-067747 and U.S. Pat. No. 5,164,881 propose a structure in which a plurality of vertical holes are formed in the above mentioned storage electrode, and JP-A-05-267614 and U.S. Pat. No. 5,150,276 propose a structure in which two annular rings and a silicon vertical fin are formed in the above mentioned capacitor contact hole.
However, in the above mentioned prior art, the following problems have been encountered.
In the above mentioned stacked capacitor forming method proposed by JP-A-06-204428 and U.S. Pat. No. 5,389,568, in order to reduce the cell size and at the same time to increase the surface of the storage electrode 8 so as to increase the storage capacitance, it is sufficient if the side wall 18 is heightened. However, if the side wall 18 is heightened, the absolute step difference between the memory cell zone and the peripheral circuit zone becomes large, with the result that it becomes difficult to pattern a wiring layer formed to extend over both the memory cell zone and the peripheral circuit zone. In addition, the higher the side wall 18 is, the weaker the strength of the side wall 18 becomes, with the result that there occurs possibility that the side wall 18 collapses.
In the approach proposed by JP-A-05-067747 and U.S. Pat. No. 5,164,881, the surface area can be increased by a number of vertical holes, but when the side wall 18 is heightened in order to further increase the surface area, the absolute step difference between the memory cell zone and the peripheral circuit zone becomes large, and it becomes difficult to pattern an overlying wiring layer, similarly to the method proposed by JP-A-06-204428 and U.S. Pat. No. 5,389,568. On the other hand, in the approach proposed by JP-A-05-267614 and U.S. Pat. No. 5,150,276, since the storage electrode is accommodated in the capacitor contact hole, the storage capacitance cannot be made so large as the former two prior art examples.